A nonvolatile memory circuit is known as a ROM (read only memory).
As well known in this technical field, the ROM (read only memory) is generally classified into a mask ROM whose content is written in a manufacturing process at a semiconductor maker and a programmable ROM (PROM) which is electrically programmable by a user.
In principle, the mask ROM can be manufactured at the lowest cost among semiconductor memories. Therefore, as the mask ROM, a type of product having a large memory capacity is commercialized. On the other hand, the programmable ROM has a characteristic that programming can be performed at a user's end. The programmable ROM is classified into a narrowly-defined PROM only once programmable by a user, an EPROM (erasable and programmable ROM) electrically programmable and erasable by ultraviolet rays or the like, and an EEPROM (electrically erasable programmable ROM) electrically erasable.
The EPROM not only allows user's programming but also erasure of all data by ultraviolet irradiation and rewriting. Since a glass window for erasure by ultraviolet rays is required, the EPROM is generally contained in a ceramic package. As the narrowly-defined PROM, there is an OTP (one time programmable ROM). Although a semiconductor chip same as that of the EPROM is contained, the OTP is not erasable by ultraviolet rays because its package has no window. A user can write information only once in each memory cell of the OTP by using a typical EPROM programmer. The OTP is higher than the mask ROM and lower than the EPROM in cost. As one type of the EEPROM, there is a flash EEPROM. The flash EEPROM is called a flash memory also and means, among PROMs as a rewritable read only memory, a memory which allows electric erasure of contents of all bits (block-by-block erasure is also possible) and rewriting.
In the EEPROM, it is required to generate a high voltage (for example, 18V) when writing data. Therefore, a charge pump circuit and a voltage booster circuit are required. On the other hand, as well known in this technical field, for the purpose of reading data from a nonvolatile memory (ROM), it is required to precharge a data line of the nonvolatile memory before actually reading the data.
The EEPROM has several types of structures which are generally classified into a floating gate type EEPROM and a MONOS-type EEPROM. The floating gate type EEPROM uses transistors each comprising a gate electrode of a double structure in which a control gate is superposed on a floating gate. By applying a high voltage to the control gate, an electric charge is injected from a substrate into the floating gate and retained. On the other hand, the MONOS-type EEPROM uses transistors each comprising a gate having a MONOS (metal/oxide film/nitride film/oxide film/silicon) structure. An electric charge is injected into a trap level existing in an oxide film/nitride film/oxide film (tunnel oxide film) structure and retained. As compared to the floating type EEPROM, the MONOS-type EEPROM is easy in manufacturing process and low in rewriting voltage. It is noted here that the MONOS is a name consisting of initial letters of a Metal-Oxide film-Nitride film-Oxide film-Semiconductor (for example, see Patent Document 1).
Hereinbelow, referring to FIGS. 1 (A) and (B), the MONOS-type EEPROM described in Patent Document 1 will be described. A MONOS transistor as a main component is formed on a p-well formed on a part of a surface of a silicon substrate which is an n-type semiconductor. Electrode regions corresponding to a drain and a source are n+-type semiconductors formed inside the p-well. The MONOS transistor has a gate which is different in structure from that of an ordinary transistor and which has a gate insulating film structure comprising three layers including a tunnel oxide film O1 formed on a surface of the p-well, a silicon nitride film N formed on the tunnel oxide film, and a top oxide film O2 further formed on the silicon nitride film. On a gate insulating film having the above-mentioned structure, a polysilicon gate electrode M is formed. The p-well, the drain, and the source of the MONOS transistor are provided with a first electrode P1, a second electrode P2, and a third electrode P3, respectively. These electrodes are connected to peripheral circuits to form the EEPROM.
When data is written into the MONOS-type EEPROM having the above-mentioned structure, the first electrode P1 is supplied with a rewriting voltage between −8 volts and −11 volts while the gate electrode M is kept at a reference potential. As a consequence, electrons move from the p-well through the tunnel oxide film O1 to the silicon nitride film N and stay in the nitride film N and at an interface between the nitride film N and the top oxide film O2. As a result, a threshold voltage of the MONOS transistor is increased and the transistor becomes non-conductive. In this writing, electric potentials of the other electrodes P2 and P3 are not important. Normally, however, it is suitable to keep these electrodes at the reference potential.
On the other hand, when the data is erased, the gate electrode M is supplied with a rewriting voltage between −8 volts and −11 volts while the first electrode P1 is kept at a reference potential. As a consequence, the electrons which stay in the gate insulating film move to the p-well and the threshold voltage of the NOMOS transistor is decreased. Then, the transistor exhibits a depression characteristic and becomes conductive. At this time also, the electric potentials of the other electrodes are normally kept at the reference potential.
As shown in a circuit diagram of FIG. 1(B), reading of data from the MONOS-type EEPROM is carried out by connecting the MONOS transistor and a normal enhancement-type MOS transistor in series and simultaneously turning on the two transistors to divide a power supply voltage. At this time, the gate electrode M and the second electrode P2 of the MONOS transistor and the first electrode P1 of the MONOS transistor are connected to the reference potential, while a gate G of the MOS transistor and a source electrode P4 of the MOS transistor are supplied with a power supply voltage between 2.5 volts and 6.5 volts. The third electrode P3 of the MONOS transistor and a drain of the MOS transistor are connected to each other to form a voltage dividing point. When data is written in the MONOS transistor, an output signal level becomes a H level. When data is not written into the MONOS transistor, an output signal level becomes a L level.
As a semiconductor integrated circuit chip, a chip including the EEPROM and an analog portion is known. For example, the semiconductor integrated circuit chip is used as a temperature compensation circuit for stabilizing an oscillation frequency of a quartz crystal oscillator dependent of a temperature. Specifically, since a quartz crystal has a temperature-dependent oscillation frequency, the quartz crystal is connected to the above-mentioned analog portion and the oscillation frequency of the quartz crystal is temperature-compensated by the analog portion. In this case, trimming information (adjusting information) is supplied from the EEPROM to the analog portion. With reference to a trimming value represented by the trimming information, the analog portion temperature-compensates the oscillation frequency of the quartz crystal. In this example, the EEPROM stores the trimming information. Therefore, the EEPROM is called a trimming memory. The semiconductor integrated circuit chip may simply be called a chip also. Further, in this example, the quartz crystal oscillator is a product and the analog portion inside the chip is a circuit to be trimmed with reference to the trimming information. Such a product requiring temperature compensation is not limited to the quartz crystal oscillator alone and includes, for example, an A/D converter, a D/A converter, and an internal power supply circuit each of which has an oscillator contained therein or the like.
Referring to FIG. 2, a conventional EEPROM module (nonvolatile memory circuit) 10 will be described. The EEPROM module 10 has a memory mat 12. The memory mat 12 is a memory cell array which comprises memory cells arranged in a two-dimensional matrix. The memory mat 12 is connected to a sense latch precharge MOS 14.
The EEPROM module 10 has an address bus 16 and a data bus 18. The address bus 16 is connected to the memory mat 12 via an X decoder 20 and a word driver 22. The data bus 18 is connected to the sense latch precharge MOS 14 via a Y switch 24. The address bus 16 is connected to the Y switch 24 via a Y decoder 26.
The EEPROM module 10 further comprises a booster circuit 28, a power-on reset circuit 30, and a control circuit 32. The power-on reset circuit 30 is connected to the control circuit 32. The control circuit 32 is connected to the address bus 16 and the data bus 18. The control circuit 32 performs input/output interface control, address bus/data bus register control, and read/write control.
For the EEPROM module 10 having the above-mentioned structure, a high-capacity type is mainstream. Therefore, the memory mat 12 occupies the highest percentage in a module area and a peripheral circuit portion (a portion except the memory mat 12) has an insignificant effect on a module size. For example, in a case where the EEPROM module 10 has a memory capacity of 64 kbits, the memory mat 12 has an occupancy of 80%, while the peripheral circuit portion has an occupancy of 20%.
Meanwhile, the above-mentioned product requiring temperature compensation starts an operation immediately after power is turned on. When trimming information is set for such a product (namely, the analog portion inside the chip), it is required, before the product starts an operation, to complete reading of the trimming information from the trimming memory and to enable or validate the trimming value represented by the trimming information.
Therefore, in the conventional technique, after the power-on reset circuit 30 is operated and before completion of reset of the chip, a reading operation of the trimming information held in an internal memory (trimming memory) is performed in response to a clock input from an internal oscillator (external oscillator) and under control of the special control circuit 32. After the trimming information is enabled or validated, reset of the chip is released. In other words, a chip reset period is extended so as to deal with the above-mentioned requirement.
FIG. 3 shows a conventional EEPROM module (semiconductor integrated circuit device) 10. In the EEPROM module 10 shown in FIG. 3, only a part necessary for power-on read in the EEPROM module 10 shown in FIG. 2 is extracted.
The EEPROM module 10 comprises a trimming memory 34 storing trimming information, the power-on reset circuit 30, an internal oscillator 36, a counter 38, and the control circuit 32.
The trimming memory 34 shown in FIG. 3 corresponds to a combination of the memory mat 12, the sense latch precharge MOS 14, the Y switch 24, the X decoder 20, and the word driver 22 in FIG. 2. The trimming memory 34 is connected to a circuit 40 to be trimmed with reference to the trimming information.
In response to power-on, the power-on reset circuit 30 starts an operation and produces a power-on reset signal to reset the control circuit 32 (flip-flops and latches inside the chip). The internal oscillator 36 oscillates an internal clock signal. The counter 38 performs a counting operation in synchronization with the internal clock signal to produce a count value. In response to the power-on reset signal, in synchronization with the internal clock signal, and with reference to the internal count value, the control circuit 32 performs chip reset control, memory select control, and data line precharge control.
FIG. 4 is a time chart (waveform diagram) for describing a data reading operation in the conventional EEPROM module (semiconductor integrated circuit device) 10 shown in FIG. 3. In FIG. 4, a first line shows a waveform of a power supply voltage (Vcc), a second line shows a waveform of a chip reset signal, a third line shows a waveform of the power-on reset signal, a fourth line shows a waveform of the internal clock signal, a fifth line shows a waveform of a memory select signal, and a sixth line shows a waveform of a data line precharge signal.
First, it is assumed that power is turned on at a time instant t1. Consequently, from the time instant t1, the power supply voltage (Vcc) is gradually increased and the chip reset signal is gradually increased also.
At a time instant t2 after lapse of a predetermined time period from the time instant t1, the power-on reset circuit 30 starts an operation and a voltage level of the power-on reset signal is gradually increased.
At a time point t3 after lapse of a predetermined time period from the time instant t1 (or a time point t3 when the voltage level of the power-on reset signal reaches a predetermined voltage), the power-on reset circuit 30 makes the power-on reset signal have a zero voltage. In other words, at the time instant t3, the power-on reset signal is shifted from a high level to a low level. That is, power-on reset is released. In response to the fall of the power-on reset signal, the control circuit 32 shifts the memory select signal for the trimming memory 34 from a low level to a high level and simultaneously receives the internal clock signal from the internal oscillator 36.
At a time instant t4, the control circuit 32 shifts the data line precharge signal from a high level to a low level. As a result, data line precharge of the trimming memory 34 is performed.
From a time instant t5 when the data line precharge signal is shifted from the low level to the high level, the control circuit 32 starts reading of the trimming information from the trimming memory 34 in synchronization with the internal clock. At a time instant t6 when reading of the trimming information is completed, the control circuit 32 shifts the memory select signal from the high level to the low level.
At a time instant t7, the control circuit 32 shifts the chip reset signal from a high level to a low level to release reset of the chip. As a result, the trimming value represented by the trimming information is enabled or validated.
Next, referring to FIG. 5 in addition to FIG. 2, an operation of the conventional EEPROM module (nonvolatile memory circuit) 10 will be described. FIG. 5 is a circuit diagram showing a memory cell for use in the memory mat 12 of the conventional EEPROM module 10 shown in FIG. 2.
First, description will be made of an operation in a case where data is read from the EEPROM module 10 and loaded (reading operation of the trimming memory 34 when power is turned on).
First, the control circuit 32 makes a MONOS gate have 0V and makes the memory cell well and the source line have 0V. Next, the control circuit 32 precharges the data line at a Vcc level. After lapse of a fixed time period (after completion of precharging), the control circuit 32 brings the data line into a floating state. The control circuit 32 makes a memory select gate have Vcc (ON).
Herein, when the MONOS gate has 0V, the MONOS transistor after erasure is in an on state so that the level of the data line is changed from Vcc to 0V. That is, memory data has “0” level. On the other hand, when the MONOS gate has 0V, the MONOS transistor after writing is in an off state so that the level (Vcc) of the data line is maintained. That is, the memory data has “1” level.
After lapse of a fixed time period (after completion of reading of the memory data), the control circuit 32 loads information of the data line into the latch. The control circuit 32 makes the memory select gate have 0V (OFF).
Next, a rewriting operation (erase/write) of the EEPROM module 10 will be described. In a case of the conventional EEPROM module 10, all memories share a common memory well. Therefore, the rewriting operation of the memory data is carried out on a word line basis. Specifically, a series of processes are required which include erasure of all memories on the same word line (“0” is written) and writing of “1” data into each memory to be written with “1” data (the state of each memory to be written with “0” data is kept unchanged).
First, the control circuit 32 latches memory data. Specifically, in order to enable rewriting on a byte-by-byte basis, the control circuit 32 is required to load all memory data on the same word line into the latch (because the “0” data is written in all memories on the same word line by the erasing operation, the memory data must be saved before writing).
Next, the control circuit 32 is supplied with memory rewriting data from a data input/output terminal and writes the memory rewriting data into the latch on a byte-by-byte basis. At this time, a part of latch data written in the above-mentioned latching of the memory data is rewritten (overwritten).
Next, the control circuit 32 erases all memories on the same word line (writes “0”). In detail, the control circuit 32 makes the memory select gate have a Vcc level (turns on). The control circuit 32 makes the MONOS gate have Vcc-13V. The control circuit 32 makes the source line have Vcc-1.5V. The control circuit 32 makes the memory cell well have Vcc-1.5V. The control circuit 32 maintains the above-mentioned state for 4 milliseconds. Consequently, all memories on the same word line are erased.
Next, the control circuit 32 terminates the erasing operation. In detail, the control circuit 32 makes the memory select gate have 0V (turns off). The control circuit 32 makes the MONOS gate have 0V. The control circuit 32 makes the source line have 0V. The control circuit 32 makes the memory cell well have 0V. The control circuit 32 maintains the above-mentioned state for 1 millisecond. Consequently, all memory cells on the same word line are returned to a standby state.
Next, the control circuit 32 writes “1” data in each memory cell in which “1” data is to be written.
It is assumed that the control circuit 32 writes “1” data in the memory cell. In this case, the control circuit 32 makes the memory select gate have a Vcc level (turns on). The control circuit 32 makes the MONOS gate have the Vcc level. The data line and the source line of each memory cell to be written with “1” data according to the data of the data latch are kept at Vcc-13V. The control circuit 32 maintains the above-mentioned state for 4 milliseconds. Consequently, “1” data is written in the memory cell in which “1” data is to be written.
It is assumed that the control circuit 32 does not write “1” data in the memory cell. In other words, it is assumed that the control circuit 32 makes the “0” data be held in the memory cell. In this case, the control circuit 32 makes the memory select gate have the Vcc level (turns on). The control circuit 32 makes the MONOS gate have the Vcc level. In the memory cell to hold “0” data according to the data of the data latch, the data line is kept at Vcc-1.5V and the source line is brought into a floating state. The control circuit 32 maintains the above-mentioned state for 4 milliseconds. Consequently, “0” data is held in the memory cell in which “1” data is not to be written.
Then, the control circuit 32 terminates the erasing operation. Specifically, the control circuit 32 makes the memory select gate have 0V (turns off). The control circuit 32 makes the MONOS gate have 0V. The control circuit 32 makes the source line have 0V. The control circuit 32 makes the memory cell well have 0V. The control circuit 32 maintains the above-mentioned state for 1 millisecond. Consequently, all memory cells on the same word line are returned to the standby state.    Patent Document 1: WO93/11509